The present invention generally relates to thermal management of electronic circuit components. More particularly, this invention relates to a circuit board-heat sink structure with an interior cavity containing a surface-mount device thermally coupled to the heat sink to provide enhanced thermal management of the device.
A variety of approaches are known for dissipating heat generated by semiconductor devices, such as integrated circuit (IC) chips. One method is to use a flex circuit laminated or bonded to a heat sink. If the flex circuit material is sufficiently thin, this approach can employ a highly conductive path formed by plated vias through the flex circuit to the heat sink. Another method is to equip a printed circuit board (PCB) with an innerlayer heat sink that is the same size or larger than the PCB to provide a large heat sink for the entire board, and rely on conduction through the PCB material to the heat sink beneath. High-power IC chips, such as power flip chips, are often mounted to substrates formed of a ceramic material such as alumina (Al2O3) or another ceramic material.
Laminate-type ceramic substrates known as low temperature co-fired ceramics (LTCC) have a number of process-related advantages over conventional ceramic substrates. LTCC substrates are conventionally made up of multiple green tapes containing a mixture of glass and ceramic fillers in an organic binder. The tapes are collated (stacked), laminated, and then fired (co-fired), during which the organic binders within the laminate stack are burned off and the remaining materials form, according to the combined composition, a monolithic ceramic substrate. Though having the above-noted processing advantages, LTCC substrates have relatively low thermal conductivities, typically about 3 W/mK as compared to about 20 W/mK for alumina. Consequently, LTCC substrates have been formed with green tapes containing a metal powder to promote heat dissipation through the substrate. However, a limitation of this approach is that the resulting metal-containing layers of the LTCC substrate are also electrically conductive to some degree. As an example, U.S. Pat. No. 6,690,583 to Bergstedt et al. discloses a thermally-conductive LTCC substrate formed of a metal-containing tape and having surface cavities in which circuit devices are contained. Because of the electrical conductivity of the LTCC substrate, electrical connections must be made to the devices by depositing a dielectric layer over the substrate and the devices within its cavities, and then forming contacts through the dielectric layer to the devices. An alternative approach disclosed in U.S. Pat. No. 5,386,339 to Polinski, Sr., is to form a limited thermally-conductive path through an otherwise conventional (dielectric) LTCC by defining a hole in a stack of dielectric green tapes, and then filling the hole with green tapes containing a thermally conductive material. On firing, the tapes form an LTCC substrate in which a vertical thermally-conductive path is present for conducting heat through the thickness of the substrate.
In other applications where individual layers of an LTCC substrate are to carry conductor patterns, resistors, etc., each ceramic layer is formed by a green tape containing only a mixture of glass and ceramic fillers in a binder. Thick-film conductors, resistors, etc., are printed on individual tapes prior to collating and laminating the tapes. The tapes, along with their conductors and resistors, are then co-fired, during which their respective binders burn off and the remaining materials form, according to their compositions, ceramic (dielectric) and metallic (conductive) materials. Because of the circuit components and their associated interconnect vias within the LTCC substrate, improved thermal conductivity cannot be obtained by the use of metal-containing ceramic layers. A solution to this problem is represented in FIG. 1, and involves forming multiple vias 116 through the thickness of an LTCC substrate 110 to conduct heat in a vertical direction from a die-and-wire type power chip 114. The thermal vias 116 are formed by punching vias in each green tape and then filling the vias with a metal such as silver prior to printing the conductors, resistors, etc. Interconnect vias 118 required to electrically interconnect components on different layers of the LTCC substrate 110 can be formed and filled at the same time as the thermal vias 116. The tapes are then laminated so that the filled vias are aligned to form through-vias, after which the tapes are fired such that the via fill material is co-fired along with conductor and resistor materials printed on surfaces of individual tapes. The entire LTCC substrate 110 (composed of bonded ceramic layers 112) is then bonded with an adhesive 120 to a heat sink 122 so that the thermal vias 116 conduct heat from the chip 114 to the heat sink 122.
While able to promote the conduction of heat away from power devices, thermal vias incur additional processing and material costs, reduce routing density, and can limit design flexibility. Furthermore, thermal vias may be inadequate to achieve suitable thermal management of certain power devices, particularly devices of the flip-chip type. For example, thermal vias alone can be inadequate because the solder bumps of a flip-chip device provide the primary thermal path from the device through the substrate. Compared to the overall die size, the contact area of each bump is relatively small, such that the bumps provide a limited thermal path to the substrate. Furthermore, the number of thermal vias that can be employed to conduct heat to and through the substrate is limited by the number of solder bumps and the configuration of the solder bump pattern. In addition, the use of thermal vias is complicated by the fact that the solder bumps usually require electrical isolation as a result of also providing the electrical connection between the device and the substrate.
In view of the above, further improvements in the construction and processing of LTCC substrates would be desirable to improve thermal management of power IC's, and particularly flip-chip power IC's, while retaining the process-related advantages of LTCC's.